In Real Life: NE555 Outputs

I was working on simple flyback driver for my HV DC supply and realized that I need some kind of a MOSFET driver. I used the excellent TC4429 in the past, but the x5 relative cost of it compared to NE555 makes me wonder if the famous chip is reliable enough to do the same task.

In this post, I test the effect of decoupling cap on supply and control voltage pins, and the effect of tied pin3 and pin7, the phase difference of both output, and the speed of internal comparator and reset pin.

So, this is my attempt of probing the pin3 output waveform, using 12V SLA and DS1102E. :)

To test the chip, I configured it as simple one-stage ring oscillator.

The first test, the supply voltage decoupling capacitor.

This is the barebone circuit. The simplicity of the circuit proved on breadboard.

This is the pin3 output of the chip, running at ~228kHz, with ~97% duty cycle.

Overshoot is also visible.

It is so tempting to add a power supply decoupling capacitor just to see the impact on the output.

100uF cap added to supply pin 1 and 8.

Clearly, the overshoot minimized and frequency seems to be raised by ~17kHz, making total of ~246kHz. 

Let's see it in detail of various cap effect.

The chip with 100nF decoupling cap.

 The chip with 180pF decoupling cap.

 This is the output without any decoupling cap.

 The output with 100uF cap.

The addition of the cap shown to be beneficial to the output performance. Especially both rise and fall time, which had improvement of 14nS and 3nS respectively.

 The output with 180pF. It overshoots even higher than before, maybe caused by the cap resonating with supply leads.

The output with 100nF decoupling cap. This one is captured at the wrong moment. The curve super imposed on each other. In reality, it is close to 100uF output. 

The output with 100nF and 100uF combined. Better performance than separated ones, gain of 2nS and 1nS for rise and fall time. This is the fastest transition that I can get: 25nS of rise and 19nS of fall.

So, the decoupling capacitor conclusion:

-Will aid output transition by 'stiffening' supplied power source.

-Smaller cap will worsen overshoot.

-Due to intrinsic ESR, ideal cap would be the combination of both electrolytic and ceramic cap, e.g. in this case, 100uF and 100nF. (But I bet 1uF and 100nF do work too.)

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Next, let's test the effect of decoupling cap on control-voltage 5th-pin of the chip.

I've seen a lot circuit online that ignore this pin and act like it does not exist. This is a bad practice of course because it effects both comparators' reference voltage in the chip.

In my test, the only parameter that is changed is only output frequency. 

Only three variation made, the cap on ground, on Vcc, and on both Gnd and Vcc.

The cap with ground referenced.

The cap with Vcc referenced.

The cap with both Vcc and ground referenced. Both caps are 100nF.

These are the resulting waveform.

This is for Vcc referenced cap. Positive and Negative width of 3.880uS and 110.0nS.

This is for Gnd referenced cap. Positive and Negative width of 3.860uS and 120.0nS.

This one is for no cap. Positive and Negative width of 3.930uS and 120.0nS.

The frequency increased when decoupling cap is used. In my test, gain of -Wid 10nS and +Wid 70nS achieved. 

Using both sides for the cap seems to yield no difference to the ground referenced ones.

Conclusion for control-voltage pin capacitor:

-Frequency increased might translates to the dampened effect of hysteresis of the internal comparator. 

-Ground referenced capacitor seems to behave better than the Vcc referenced ones.

-For MOSFET driving purposes, this means faster signal propagation delay with minimized phase shift. 

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Next test is, the effect if tied pin3 and pin7 of the chip.

The 3rd pin is the dedicated 'output' for the chip, it has a push-pull output, while the 7th pin is a 'discharge' pin, which has only an open-collector output. 

These two pins have the same output phase, so, combining them supposed not to cause any problem, right?

Let's find out. :)

This is the overview of tied output.

This is the overview of untied output.

Notice that the tied output have a bit of 'bulge' to it; having a prolonged overshoot.

I zoomed in for better detail.

This is pin3 and pin7 tied together.

This is solely pin3 output.

So, it is clear that the pin7 really does 'fighting' with pin3. Pin7 transistor seems to switch off a bit slow, causing the rise time suffers. The fall time doesn't affected, it stays at 23nS, but the rise time, from 29nS to 108nS, is a significant change. But bear in mind, this is unloaded output.

Now, I add a capacitive load of 2nF to the output.

The capacitive load is in orange. :)  

Overview of untied output with capacitive loading.

Overview of tied output with capacitive loading.

Close-up of  untied output with capacitive loading.

Close-up of  tied output with capacitive loading.

It is shown that even with detrimentally slowed rise time, it has improved the fall time of from 60ns to 45ns.

Also visible, the falling curve is much sharper and more close towards the ground.

So, I thought, if the discharge-pin really does improve the falling-edge, why not just put a diode to isolated it from damaging the rising-edge?

1N4148 on pin3 and pin7.

Turns out, it failed. :( 

Adding a diode, with the cathode facing 3rd pin, nothing change. It behave like untied output.

Conclusion on tied output:

-It improves falling edge at the expense of damaging rising-edge.

-But, it also make the chip more capable of sinking current  which means, output is much closer to ground.

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Another test, the non-inverting version of the circuit. 

I saw this back in old days and thought, that is a creative use of the reset pin.

What I've done here is just use a generic NPN transistor to invert the output of the chip, then, just feed it directly to the pulled-up 4th 'reset' pin. The 2nd and 6th pin is grounded of course.

The reset-pin oscillator circuit, with capacitive loading.

 Overview of the oscillator output.

Close-up of 3rd-pin output. 

Close up of tied 3rd and 7th pin output.

Although it's working at higher speed of ~334kHz, the output suffers by slower slew rate for both edges.

It's worsen with tied output, albeit the +Width is much shorter. 

Conclusion for 'reset' pin oscillator:

-It does oscillate faster than previous circuit.

-But, it has the worse signal step-response in my test.

-Still usable at slow frequency.

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Final test, the phase difference of both 3rd 'output' pin and 7th 'discharge' pin.

This is just for fun, comparing the time delay of the 'discharge' pin to turn off.

Output of the 3rd pin.

Output of the 7th pin, with 10kR pull-up resistor. 

The 7th pin output is much smoother when rising, with no visible overshoot.

Conclusion for output phase difference:

-The 7th pin slow to turn off by 400ns.

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Post summary:
NE555 could be deployed as MOSFET driver for anything below ~50kHz (arbitrarily chosen).
It is recommended to:
-Use decoupling cap for both power supply and control voltage pins.
-Tied 3rd and 7th pin is optional, but it will promotes better turn-off performance.
-It could be use as both inverting and non-inverting driver, albeit performing better for the latter. 

It is amazing how this popular chip can teach me a lot in electronics signal integrity, which includes the importance of decoupling cap, signal transition and propagation time delay, current sourcing and sinking, phase difference, voltage overshoot, hysteresis, push-pull vs. open-collector output, and many more. :)